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  a dsp microcomputer information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringeme nts of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel:781/329-4700 www.analog.com fax:781/326-8703 ? analog devices, inc., 2002 rev. 0 s sharc is a registered trademark of analog devices ADSP-21161N summary high performance 32-bit dsp?applications in audio, medical, military, wi reless communications, graphics, imaging, motor-control, and telephony super harvard architecture?four independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead i/o code-compatible with all other sharc family dsps single-instruction-multiple-data (simd) computational architecture?two 32-bit ieee floating-point computation units, each with a multiplier, alu, shifter, and register file serial ports offer i 2 s support via 8 programmable and simultaneous receive or transmit pins, which support up to 16 transmit or 16 receive channels of audio integrated peripherals?integrated i/o processor, 1 mbit on-chip dual-ported sra m, sdram controller, glueless multiprocessing features, and i/o ports (serial, link, external bus, spi, and jtag) ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit floating-point formats key features 100 mhz (10 ns) core instruction rate single-cycle instruction execution, including simd operations in both computational units 600 mflops peak and 400 mflops sustained performance 225-ball 17x17mm mbga package functional block diagram alu mult data register file (pey) 16 x 40-bit barrel shifter barrel shifter alu data register file (pex) 16 x 40-bit timer instruction cache 32 x 48-bit dag1 8x4x32 program sequencer dag2 8x4x32 32 pm address bus dm address bus 32 bus connect (px) pm data bus dm data bus 64 64 core processor spi ports (1) serial ports (4) link ports (2) dma controller 5 16 20 4 iop registers (memory mapped) control, status, & data buffers i/o processor two independent dual-ported blocks addr data data data addr addr data addr processor port i/o port b l o c k 0 b l o c k 1 dual-ported sram host port addr bus mux multiprocessor interface data bus mux 32 24 external port 6 12 8 jtag test & emulation gpio flags sdram controller ioa 18 iod 64
?2? ADSP-21161N rev. 0 key features (continued) 1 mbit on-chip dual-ported sra m (0.5 mbit block 0, 0.5 mbit block 1) for independen t access by core processor and dma 400 million fixed-point macs sustained performance dual data address generators (dags) with modulo and bit-reverse addressing zero-overhead looping with single-cycle loop setup, providing efficient program sequencing ieee 1149.1 jtag standard test access port and on-chip emulation single instruction multiple data (simd) architecture provides: two computational processing elements concurrent execution?each processing element executes the same instruction, but operates on different data code compatibility?at assembly level, uses the same instruction set as other sharc dsps parallelism in buses and computational units allows: single-cycle execution (with or without simd) of: a multiply operation, an alu operation, a dual memory read or write, and an instruction fetch transfers between memory and core at up to four 32-bit floating- or fixed- point words per cycle, sustained 1.6 gbytes/s bandwidth accelerated fft butterfly computation through a multiply with add and subtract dma controller supports: 14 zero-overhead dma channels for transfers between ADSP-21161N internal memory and external memory, external peripherals, host processor, serial ports, link ports, or serial peripheral interface (spi-compatible) 64-bit background dma transf ers at core clock speed, in parallel with full-speed processor execution 800 mbytes/s transfer rate over iop bus host processor interface to 8-, 16-, and 32-bit microprocessors; the host can directly read/write ADSP-21161N iop registers 32-bit (or up to 48-bit) wide synchronous external port provides: glueless connecti on to asynchronous, sbsram and sdram external memories memory interface supports programmable wait state generation and wait mode for off-chip memory up to 50 mhz operation for non-sdram accesses 1:2, 1:3, 1:4, 1:6, 1:8 cloc k into core clock frequency multiply ratios 24-bit address, 32-bit data bus. 16 additional data lines via multiplexed link port data pins allow complete 48-bit wide da ta bus for single-cycle external instruction execution direct reads and writes of iop registers from host or other 21161n dsps 62.7 mega-word address range for off-chip sram and sbsram memories 32-48, 16-48, 8-48 executio n packing for executing instruction directly from 32-bit, 16-bit, or 8-bit wide external memories 32-48, 16-48, 8-48, 32-32/6 4, 16-32/64, 8-32/64, data packing for dma transfers directly from 32-bit, 16-bit, or 8-bit wide external memories to and from internal 32-, 48-, or 64-bit internal memory can be configured to have 48-bit wide external data bus, if link ports are not used. the link port data lines are multiplexed with the data lines d0 to d15 and are enabled through control bits in syscon sdram controller for glueless interface to low cost external memory zero wait state, 100 mhz operation for most accesses extended external memory banks (64 m-words) for sdram accesses page sizes up to 2048 words an sdram controller supports sdram in any and all memory banks support for interface to run at core clock and half the core clock frequency support for 16 mbits, 64 mbits, 128 mbits, and 256 mbits with sdram data bus configurations of x4, x8, x16, and x32 254 mega-word address range for off-chip sdram memory multiprocessing support provides: glueless connection for scal able dsp multiprocessing architecture distributed on-chip bus arbitration for parallel bus connect of up to six ads p-21161ns, global memory and a host two 8-bit wide link ports for point-to-point connectivity between ADSP-21161Ns 400 mbytes/s transfer rate over parallel bus 200 mbytes/s transfer rate over link ports serial ports provide: four 50 mbit/s synchronous serial ports with companding hardware 8 bi-directional serial data pins, configurable as either a transmitter or receiver i 2 s support, programmable direction for 8 simultaneous receive and transmit channels, or up to either 16 transmit channels or 16 receive channels tdm support for t1 and e1 interfaces, and 128 tdm channel support for newer telephony interfaces such as h.100/h.110 companding selection on a per channel basis in tdm mode serial peripheral interface (spi) slave serial boot through sp i from a master spi device full-duplex operation master-slave mode multi-master support open drain outputs programmable baud rates, clock polarities and phases 12 programmable i/o pins 1 programmable timer general description the ADSP-21161N sharc dsp is the first low cost derivative of the adsp-21160 featuring analog devices super harvard architecture. easing portability, the ADSP-21161N is source code compatible with the adsp-21160 and with first generation
?3? rev. 0 ADSP-21161N adsp-2106x sharcs in sisd (single instruction, single data) mode. like other sharcs, the ADSP-21161N is a 32-bit processor that is optimize d for high performance dsp applications. the ADSP-21161N includes a 100 mhz core, a dual-ported on-chip sram, an integrated i/o processor with multiprocessing support, and multip le internal buses to eliminate i/o bottlenecks. the ADSP-21161N offers a single-instruction-multiple-data (simd) architecture, which was first offered in the adsp-21160. using two computational units (adsp-2106x sharcs have one), the adsp-2 1161n can double cycle per- formance versus the adsp-2106x on a range of dsp algorithms. fabricated in a state of the art, high speed, low power cmos process, the ADSP-21161N has a 10 ns instruction cycle time. with its simd computational hardware running at 100 mhz, the ADSP-21161N can perform 600 million math operations per second. table 1 shows performance benchmarks for the ADSP-21161N. the ADSP-21161N continues sharc?s industry-leading standards of integration for dsps , combining a high performance 32-bit dsp core with integrated, on-chip system features. these features include a 1 mbit dual ported sram memory, host processor interface, i/o processor that supports 14 dma channels, four serial ports, two link ports, sdram controller, spi interface, external parallel bus, and glueless multiprocessing. the block diagram of the ADSP-21161N on page 4 , illustrates the following architectural features: ? ? (1 2) ? ? 2 ? ? (1 ) ? ? ? ? 21161 ? ? ? ? ? ? ? 12 1 . . 21161 21161 2116 . 21161 21160 21060 21061 21062 21065. simd computational engine the ADSP-21161N contains two computational processing elements that operate as a single instruction multiple data (simd) engine. the processing el ements are referred to as pex and pey, and each contains an alu, multiplier, shifter, and register file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instruction is executed in both pro- cessing elements, but each pro cessing element operates on different data. this architecture is efficient at executing math intensive dsp algorithms. entering simd mode also has an effect on the way data is trans- ferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the pr ocessing elements. because of this requirement, entering simd mode also doubles the bandwidth between memory and the processing elements. when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the register file. independent, parallel computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform single-cycle instructions. the three units with in each processing element are arranged in parallel, maximizi ng computational throughput. single multi-function instructions execute parallel alu and multiplier operations. in simd mode, the parallel alu and mul- tiplier operations occur in bo th processing elements. these computation units support ieee 32-bit single-precision float- ing-point, 40-bit extended preci sion floating-point, and 32-bit fixed-point data formats. table 1. benchmarks (at 100 mhz) benchmark algorithm speed (at 100 mhz) 1024 point complex fft (radix 4, with reversal) 1 1 assumes two filters in multichannel simd mode. 92 s fir filter (per tap) 1 5 ns iir filter (per biquad) 1 20 ns matrix multiply (pipelined) [3x3] 1 1 5 0 () 0 5 00
?4? ADSP-21161N rev. 0 data register file a general-purpose data register fi le is contained in each process- ing element. the register files transfer data between the computation units and the data buses, and store intermediate results. these 10-port, 32-register (16 primary, 16 secondary) register files, combined with the adsp-2116x enhanced harvard architecture, allow unconstrained data flow between computa- tion units and internal memory. the registers in pex are referred to as r0-r15 and in pey as s0-s15. single-cycle fetch of instruction and four operands the ADSP-21161N features an enhanced harvard architecture in which the data memory (dm) bus transfers data and the program memory (pm) bus transfers both instructions and data (see figure 1 on page 4 ). with the ADSP-21161N?s separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and an instruct ion (from the cache), all in a single cycle. instruction cache the ADSP-21161N includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. the cache is select ive?only the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full-speed execution of co re, looped operations such as digital filter multiply-accumulate s, and fft butterfly processing. data address generators with hardware circular buffers the ADSP-21161N?s two data address generators (dags) are used for indirect addressing and implementing circular data buffers in hardware. circular buffers allow efficient programming of delay lines and other data struct ures required in digital signal processing, and are commonly used in digital filters and fourier transforms. the two dags of the ADSP-21161N contain suffi- cient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). the dags automati- cally handle address pointer wrap-around, reduce overhead, increase performance, and simplify implementation. circular buffers can start and end at any memory location. figure 1. system dma device (optional) data clkout dmar1-2 dmag1-2 addr data host processor interface (optional) 3 12 clock clkin xtal irq2-0 2 clk_cfg1-0 eboot lboot flag11-0 timexp clkdbl reset jtag 7 sbts adsp-21161 bms link devices (2 max) (optional) lxclk lxack lxdat7-0 sclk0 d0b d0a fs0 serial device (optional) cs boot eprom (optional) addr memory and peripherals (optional) oe data cs rd ras ack br1-6 rpba id2-0 pa hbg hbr sdwe ms3-0 wr data47-16 data addr cs ack we addr23-0 d a t a c o n t r o l a d d r e s s brst sdram (optional) sclk1 d1b d1a fs1 serial device (optional) sclk2 d2b d2a fs2 serial device (optional) sclk3 d3b d3a fs3 serial device (optional) spiclk miso mosi spids spi compatible device (host or slave) (optional) data cas ras dqm we addr cs a10 cke clk dqm cas redy sdcke sda10 sdclk1-0 rstout
?5? rev. 0 ADSP-21161N flexible instruction set the 48-bit instruction word accommodates a variety of parallel operations, for concise programming. for example, the ADSP-21161N can conditionally execu te a multiply, an add, and a subtract in both processing elements, while branching, all in a single instruction. ADSP-21161N memory and i/o interface features the ADSP-21161N adds the following architectural features to the adsp-2116x family core: dual-ported on-chip memory the ADSP-21161N contains one megabit of on-chip sram, organized as two blocks of 0.5 mbits. each block can be config- ured for different combinations of code and data storage. each memory block is dual-ported for single-cycle, independent accesses by the core processor and i/o processor. the dual-ported memory in combination with three separate on-chip buses allow two data transfers from the core and one from the i/o processor, in a single cycle. on the ADSP-21161N, the memory can be configured as a maximum of 32k words of 32-bit data, 64k words of 16-bit data, 21k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to one megabit. all of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point formats is done in a single instruction. while each memory block can st ore combinations of code and data, accesses are most efficient wh en one block stores data using the dm bus for transfers, and the other block stores instructions and data using the pm bus for transfers. using the dm bus and pm bus, with one dedicated to each memory block, assures sin- gle-cycle execution with two data transfers. in this case, the instruction must be available in the cache. figure 2. memory map 0x000a 0000 - 0x000a 7fff (blk 1) 0x0002 8000 - 0x0002 9fff (blk 1) 0x0005 0000 - 0x0005 3fff (blk 1) 0x0010 0000 - 0x0011 ffff 0x0004 0000 - 0x0004 3fff (blk 0) 0x0008 0000 - 0x0008 7fff (blk 0) 0x0012 0000 - 0x0013 ffff 0x0014 0000 - 0x0015 ffff 0x0016 0000 - 0x0017 ffff 0x001a 0000 - 0x001b ffff 0x0000 0000 - 0x0001 ffff 0x0002 0000 - 0x0002 1fff (blk 0) 0x0020 0000 bank 1 ms0 bank 2 ms1 bank 3 ms2 ms3 iop registers long word addressing short word addressing normal word addressing address bank 0 0x03ff ffff (sdram) 0x00ff ffff (non-sdram) 0x0400 0000 0x07ff ffff (sdram) 0x04ff ffff (non-sdram) 0x0800 0000 0x0bff ffff (sdram) 0x08ff ffff (non-sdram) 0x0c00 0000 0x0fff ffff (sdram) 0x0cff ffff (non-sdram) note: bank sizes are fixed 0x0018 0000 - 0x0019 ffff internal memory space multiprocessor memory space address iop registers of ADSP-21161N with id = 001 iop registers of ADSP-21161N with id = 010 iop registers of ADSP-21161N with id = 011 iop registers of ADSP-21161N with id = 100 iop registers of ADSP-21161N with id = 101 iop registers of ADSP-21161N with id = 110 reserved 0 x 001c ffff 0 x 001f ffff external memory space
?6? ADSP-21161N rev. 0 off-chip memory and peripherals interface the ADSP-21161N?s external port provides the processor?s interface to off-chip memory and peripherals. the 62.7-mega- word off-chip address space (254-megaword if all sdram) is included in the ADSP-21161N?s unified address space. the separate on-chip buses?for pm addresses, pm data, dm addresses, dm data, i/o addresses, and i/o data?are multi- plexed at the external port to create an external system bus with a single 24-bit address bus and a single 32-bit data bus. every access to external memory is based on an address that fetches a 32-bit word. when fetching an instruction from external memory, two 32-bit data locations are being accessed for packed instructions. unused link port lines can also be used as additional data lines data[0]-data[15], allowing single-cycle execution of instructions from external memory at up to 100 mhz. figure 3 on page 6 shows the alignment of various accesses to external memory. the external port supports asynchronous, synchronous, and syn- chronous burst accesses. synchronous burst sram can be interfaced gluelessly. the ADSP-21161N also can interface glue- lessly to sdram. addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. the ADSP-21161N provides programmable memory wait states and external memory acknowledge controls to allow interfacing to memory and peripherals with variable access, hold, and disable time requirements. sdram interface the sdram interface enables the ADSP-21161N to transfer data to and from synchronous dram (sdram) at the core clock frequency or one-half the core clock frequency. the syn- chronous approach, coupled with the core clock frequency, supports data transfer at a hi gh throughput?up to 400 mbytes/s for 32-bit transfers and 600 mbytes/s for 48-bit transfers. the sdram interface provides a glueless interface with standard sdrams?16 mb, 64 mb, 128 mb, and 256 mb ? and includes options to support additional buffers between the ADSP-21161N and sdram. the sdram interface is extremely flexible and provid es capability for connecting sdrams to any one of the ADSP-21161N?s four external memory banks, with up to all four banks mapped to sdram. systems with several sdram devices connected in parallel may require buffering to meet overall system timing requirements. the ADSP-21161N supports pipe lining of the address and control signals to enable such buffering between itself and multiple sdram devices. target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee 1149.1 jtag test access port of the ADSP-21161N processor to monitor and contro l the target board processor during emulation. analog devices dsp tools product line of jtag emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. the processor's jtag interface ensures that the emulator will not affect target system loading or timing. for complete information on sharc analog devices dsp tools product line of jtag emulator operation, see the appro- priate ?emulator hardware user's guide.? for detailed information on the interfacing of analog devices jtag emulators with analog devices dsp products with jtag emulation ports, please refer to engineer to engineer note ee-68, ?analog devices jtag emulation technical reference.? both of these documents can be found on the analog devices website: http://www.analog.com/dsp/tech_docs.html dma controller the ADSP-21161N?s on-chip dma controller allows zero-over- head data transfers without processor intervention. the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while the core is simul- taneously executing its program instructions. dma transfers can occur between the ADSP-21161N?s internal memory and external memory, external peripherals, or a host processor. dma transfers can also occur between the ADSP-21161N?s internal memory and its serial ports, lin k ports, or the spi-compatible (serial peripheral interface) port. external bus packing and unpacking of 16-, 32-, 48-, or 64 -bit words in internal memory is performed during dma transfer s from either 8-, 16-, or 32-bit wide external memory. fourteen channels of dma are available on the ADSP-21161N?two are shared between the spi interface and the link ports, eight via the serial ports, and four via the processor?s external port (for either host processor, other ADSP-21161Ns, memory or i/o transfers). programs can be downloaded to the ADSP-21161N using dma transfers. asyn- chronous off-chip peripherals can control two dma channels using dma request/grant lines ( dmar 1-2 dmag 1-2 o dma - dma dma dma figure 3. external data alignment options data 47-16 data 15-0 47 40 39 32 31 24 23 16 15 8 7 0 l1data[7:0] data 15-8 l0data[7:0] data7-0 p rom bo ot 8-bit packed dma data 8-bit packed instruction execution 16-bit packed dma data 1 6-bit packed instructi on ex ecuti on float or fixed, d31-d0, 32-bit packed 32-bit packed instruction 48-bit instruction fetch (no packing) extradatalinesdata[15-0] are only accessible if link ports are disabled. enable these additional data lines by selecting ipack[1:0] = 01 in sy scon
?7? rev. 0 ADSP-21161N multiprocessing the ADSP-21161N offers powerful features tailored to multiprocessing dsp systems. the external port and link ports provide integrated glueless multiprocessing support. the external port supports a unified address space (see figure 2 on page 5 ) that allows direct interprocessor accesses of each ADSP-21161N?s internal memory-mapped (i/o processor) reg- isters. all other internal memory can be indirectly accessed via dma transfers initiated via the programming of the iop dma parameter and control registers. distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing up to six ADSP-21161Ns and a host processor. master processor change over incurs only one cycle of overhead. bus arbitration is selectable as either fixed or rotating priority. bus lock allows indivisible read-modify-write sequences for semaphores. a vector interrupt is provided for interprocessor commands. maximum throughput for interprocessor data transfer is 400 mbytes/s over the external port. two link ports provide a second method of multiprocessing com- munications. each link port can support communications to another ADSP-21161N. the ADSP-21161N running at 100 mhz has a maximum throughput for interprocessor communi- cations over the links of 200 mbytes/s. the link ports and cluster multiprocessing can be used concurrently or independently. link ports the ADSP-21161N features two 8-bit link ports that provide additional i/o capabilities. with the capability of running at 100 mhz, each link port can support 100 mbytes/s. link port i/o is especially useful for point-to -point interprocessor communica- tion in multiprocessing system s. the link ports can operate independently and simultaneo usly, with a maximum data throughput of 200 mbytes/s. link por t data is packed into 48- or 32-bit words and can be directly read by the core processor or dma-transferred to on-chip memory. each link port has its own double-buffered input and output registers. clock/acknowledge handshaking controls link port tr ansfers. transfers are program- mable as either transmit or receive. serial ports the ADSP-21161N features four synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. each serial port is made up of two data lines, a clock and frame sync. the data lines can be programmed to either transmit or receive. the serial ports operate at up to half the clock rate of the core, providing each with a maximum data r a t e o f 5 0 m b i t / s. t h e s e r i a l data pins are programmable as either a transmitter or receiver, providing greater flexibility for serial communications. serial port data can be automatically transferred to and from on-chip memory via a dedicated dma. each of the serial ports features a time division multiplex (tdm) multichannel mode, where two serial ports are tdm transmitters and two serial ports are tdm receivers (sport0 rx paired with sport2 tx, sport1 rx paired with sport3 tx). each of the serial ports also support the i 2 s protocol (an industry standard interface commonly used by audio codecs, adcs and dacs), with two data pins, allowing four i 2 s channels (using two i 2 s stereo devices) per serial port, with a maximum of up to 16 i 2 s channels. the serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. for i 2 s mode, data-word lengths are selectable between 8 bits and 32 bits. serial ports offer selectable synchronization and transmit modes as well as optional -law or a-law companding. serial port clocks and frame syncs can be inte rnally or externally generated. serial peripheral (compatible) interface serial peripheral interface (spi) is an industry standard synchro- nous serial link, enabling the ADSP-21161N spi-compatible port to communicate with other spi-compatible devices. spi is a 4-wire interface consisting of two data pins, one device select pin, and one clock pin. it is a full-duplex synchronous serial interface, supporting both master and slave modes. the spi port can operate in a multi-master envi ronment by interfacing with up to four other spi-compatible devices , either acting as a master or slave device. the ADSP-21161N spi-compatible peripheral implementation also features programmable baud rate and clock phase/polarities. the ADSP-21161N spi-compatible port uses open drain drivers to support a multi-master configuration and to avoid data contention. host processor interface the ADSP-21161N host interface allows easy connection to standard 8-bit, 16-bit, or 32-bit microprocessor buses with little additional hardware required. the host interface is accessed through the ADSP-21161N?s external port. four channels of dma are available for the host interface; code and data transfers are accomplished with low software overhead. the host processor requests the ADSP-21161N?s external bus with the host bus request ( hbr hbg red t iop adsp-21161 dma dma dma x general purpose i/o ports the ADSP-21161N also contains twelve programmable, general purpose i/o pins that can function as either input or output. as output, these pins can signal peri pheral devices; as input, these pins can provide the test for conditional branching. program booting the internal memory of the ADSP-21161N can be booted at system power-up from either an 8-bit eprom, a host processor, the spi interface, or through one of the link ports. selection of the boot source is controlled by the boot memory select ( bms eboot eprom b l/h b lboot - 16- 32- phased locked loop and crystal double enable the ADSP-21161N uses an on-chi p phase locked loop (pll) to generate the internal clock for the core. the clk_cfg[1:0] pins are used to select ratios of 2:1, 3:1, and 4:1. in addition to the pll ratios, the clkdbl t 1x/2x clki clkdbl pll
?8? ADSP-21161N rev. 0 the synchronous external port op erates. with the combination of clk_cfg[1:0] and clkdbl 21 31 41 61 1 clki s 10 p 21 power supplies the ADSP-21161N has separate power supply connections for the internal (v ddint ), external (v ddext ), and analog (av dd /agnd) power supplies. the in ternal and analog supplies must meet the 1.8 v requirement. the external supply must meet the 3.3 v requirement. all external supply pins must be connected to the same supply. figure 4. shared memory multiprocessing system ack oe addr data cs we global memory and peripherals (optional) c o n t r o l adsp-21161 #1 addr23-0 control adsp-21161 #3 id2-0 reset clkin 3 adsp-21161 #4 clock addr data sdram (optional) cs addr data boot eprom (optional) id2-0 reset clkin c o n t r o l a d d r e s s d a t a c o n t r o l a d d r e s s d a t a control adsp-21161 #2 id2-0 reset clkin 2 1 addr data host processor interface (optional) we ras cas dqm clk a10 cke cs data47-16 sdwe ras cas dqm sdclk[1-0] sda10 sdcke br6-2 rd ms3-0 sbts cs ack br1 redy hbg hbr wr bms addr23-0 reset data47-16 addr23-0 data47-16
?9? rev. 0 ADSP-21161N note that the analog supply (av dd ) powers the ADSP-21161N?s clock generator pll. to produce a stable clock, provide an external circuit to filter the power input to the av dd pin. place the filter as close as possible to the pin. for an example circuit, see figure 5 . to prevent noise coupling, use a wide trace for the analog ground (agnd) signal a nd install a decoupling capacitor as close as possible to the pin. development tools the ADSP-21161N is supported with a complete set of software and hardware development tool s, including analog devices emulators and visualdsp++ 1 development environment. the same emulator hardware that supports other adsp-21xxx dsps, also fully emulates the ADSP-21161N. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/lib rary builder), a linker, a loader, a cycle-accurate instruction-level simulator, a c/c++ compiler, and a c/c++ run-time library that includes dsp and mathemat- ical functions. two key points for these tools are: ? 21161 + + ++ 21161 . ++ . ? 2106 2106 21161. ++ ++ ? ++ ( ) ? ? ? ? ? ? ? ++ . 21 ++ . ? . ? . 11.1 21161 . . . 21 . 21 . . designing an emulator-compatible dsp board (target) the analog devices dsp tools family of emulators are tools that every dsp developer needs to test and debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. the emulator uses the tap to access the internal features of the dsp, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the dsp must be halted to send data and commands, but once an operation has been completed by the emulator, the ds p system is set running at full speed with no impact on system timing. to use these emulators, the targ et?s design must include the interface between an analog devices jtag dsp and the emulation header on a custom dsp target board. target board header the emulator interface to an analog devices jtag dsp is a 14-pin header, as shown in figure 6 . the customer must supply this header on the target board in order to communicate with the emulator. the interface consists of a standard dual row 0.025" square post header, set on 0.1" 0.1 0.25. . . ( ) . 0.15 0.10 . 6 . trst emu figure 5. analog power (av dd ) filter circuit 1 visualdsp++ is a registered tra demark of analog devices, inc. 10  v ddint 0.1  f 0.01  f agnd av dd
?10? ADSP-21161N rev. 0 emulator). there are also s econdary jtag signals btms, btck, btdi, and btrst - w btms btck btrst btdi t tag dsp r tag jtag emulator pod connector figure 8 details the dimensions of the jtag pod connector at the 14-pin target end. figure 9 displays the keep-out area for a target board header. the keep-out area allows the pod connector to properly seat onto the target board header. this board area should contain no components (chi ps, resistors, capacitors, etc.). the dimensions are referenced to the center of the 0.25" square design-for-emulation circuit information for details on target board desi gn issues including: single processor connections, multiproce ssor scan chains, signal buff- ering, signal termination, and emulator pod logic, see the ee-68: analog devices j tag emulation technical reference on the analog devices website?use site search on ?ee-68? (www.analog.com). this document is updated regularly to keep pace with improvements to emulator support. additional information this data sheet provides a general overview of the ADSP-21161N architecture and functionality. for detailed information on the adsp-2116x family core architecture and instruction set, refer to the ADSP-21161N sharc dsp hardware reference and the 21160 sharc dsp instruction set reference. pin function descriptions ADSP-21161N pin definitions are listed below. inputs identified as synchronous (s) must meet timing requirements with respect to clkin (or with respect to tck for tms, tdi). inputs identified as asynchronous (a) can be asserted asynchronously to clkin (or to tck for trst t ddet gd x ? 20 0 ( 21161 20 00.) ? pa ack rd wr dmarx dmagx id20 00x ote t - adsp-21161 dsp id20 00x ? 0 ( 0) ( ADSP-21161N sharc dsp hardware reference. ) ? emu tms trst tdi ote t - figure 6. jtag target board connector for jtag equipped analog devices dsp (jumpers in place) figure 7. jtag target board connector with no local boundary scan top view 13 14 11 12 910 78 56 34 12 emu gd tms tck trst tdi td gd ke pi btms btck btrst btdi gd tp iew 2 0 2 emu gd tms tck trst tdi td gd ke pi btms btck btrst btdi gd figure 8. jtag pod connector dimensions figure 9. jtag pod co nnector keep-out area 0.64" 0.88" 0.24" 0.10" 0.1 5"
?11? rev. 0 ADSP-21161N the following symbols appear in the type column of table 2 : a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open drain, and t = three-state (when sbts adsp-21161 u sharc adsp-21161 50 ? . . . 2. 20 . 21161 . 21161 ( ). 21161 . 20 . 21161 2000. 16 . 21161 . . 16 . 21161 2000. data[15:8] pins (multiplexed with l1data[7:0]) can also be used to extend the data bus if the link ports are disabled and will not be used . in addition, data[7:0] pins (multiplexed with l0data[7:0]) can also be used to extend the data bus if the link ports are not used. this allows execution of 48-bit instructions from external sbsram (system clock speed-external port), sram (system clock speed-external port) and sdram (core clock or one-half the core clock speed). the ipackx instruction packing mode bits in sysc on should be set correctly (ipack1-0 = 0x1) to enable this full instruction width/no-packing mode of operation. ms 3-0 i/o/t m s l t - x m x 16 m -sdram 64 m sdram t ms 3-0 i ms 3-0 i ms 3-0 - clki ack i msx sharc t 24 26 26 2 ms 3-0 rd i/o/t m r s rd adsp-21161 x iop adsp-21161 ex adsp-21161 rd adsp-21161 iop i rd rd 20 ? 20 00. wr i/o/t m w l s wr adsp-21161 x iop adsp -21161 ex wr adsp-21161 iop i wr wr 20 ? 20 00.
?12? ADSP-21161N rev. 0 brst i/o/t sequential burst access. brst is asserted by ADSP-21161N to indicate that data associated with consecutive ad dresses is being read or written. a slave device samples the initial address and incr ements an internal address counte r after each transfer. the incre- mented address is not pipeli ned on the bus. a master ADSP-21161N in a multiprocessor environment can read slave external port buffe rs (epbx) using the burst protocol. brst is asserted after the initia l access of a burst transfer. it is asserted for every cycle after that, except for the last data re quest cycle (denoted by rd wr brst a dsp brst t adsp-21161 id2-000x ack i/o/s m a ex - ack x ack i/o - x t adsp-21161 ack iop ack 20 ? 20 00. sbts i/s s b t-s ex sbts x i adsp-21161 x sbts sbts sbts / adsp-21161 cas i/o/t sdram c a s i ras msx sdwe sdclkx sda10 sdram ras i/o/t sdram r a s i cas msx sdwe sdclkx sda10 sdram sdwe i/o/t sdram w e i cas ras msx sdclkx sda10 sdram dqm o/t sdram d m i dqm sdram - sdclk0 i/o/s/t sdram c o 0 c sdram sdclk1 o/s/t sdram c o 1 a sdram sdram - e sdclk1 sdclkx - sdcke i/o/t sdram c e e clk sdram sda10 o/t sdram a10 p e sdram -sdram irq 2-0 i/a i r l t clki - - lag11-0 i/o/a p e a a x timep o t ex a tcout hbr i/a h b r m adsp-21161 x w hbr adsp-21161 hbg t adsp-21161 hbr ad sp-21161 br6-1 hbg i/o h b g a hbr x hbg adsp-21161 hbr i hbg adsp-21161 a hbr hbg hbg 1 ck 1 clki t hbg 20 ? 50 ? . 2. ()
?13? rev. 0 ADSP-21161N cs i/a c s a adsp-21161 red o o/d h b a t adsp-21161 red iop cs hbr dmar1 i/a dma r 1 dma c 11 a x dma dmar1 20 ? 20 00. dmar2 i/a dma r 2 dma c 12 a x dma dmar2 20 ? 20 00. dmag1 o/t dma g 1 dma c 11 a ad sp-21161 dma x d dmag1 20 ? 20 00. dmag2 o/t dma g 2 dma c 12 a adsp-21161 dma x d dmag2 20 ? 20 00. br 6-1 i/o/s m b r u ad sp-21161 a adsp- 21161 brx id2-0 i x adsp-21161 brx br x bmstr o b m o i adsp-21161 x t adsp-21161 bmstr i - id 000 id2-0 i m id d br1 - br6 adsp-21161 id 001 br1 id 010 br2 u id 000 id 001 - t - rpba i/s r p b a s w rpba w rpba x t adsp-21161 i rpba clki adsp-21161 pa i/o/t p a a pa adsp-21161 dma x pa adsp-21161 i pa pa 20 ? 20 00. ( 0 1 2 ). . . . ( 0 1 2 ) . . . . ( 0 1 2 ). . . ( 0 1 2 ). . . . 2. ()
?14? ADSP-21161N rev. 0 spiclk i/o serial peripheral interface clock signal . driven by the master, th is signal controls the rate at which data is transferred. the master may transmit data at a variety of baud rates. spiclk cycles once for each bit transmitted. spiclk is a gated clock that is active during data transfers, only for the length of the transf erred word. slave devices ignore the serial clock if the slave select input is driven inactive (h igh). spiclk is used to shift out and shift in the data driven on the miso and mosi lines. the data is always shifted out on one clock edge of the clock and sampled on the opposite edge of the clock. clock polarity and clock phase relative to data are programmable into the spictl control register and define the transfer format. spiclk has an internal pull-up resistor. spids i s p i s d s a t i - spids i - - - lag3-0 ddet adsp-21161 adsp-21161 spi adsp-21161 lag3-0 spids adsp-21161 spi mosi i/o / spi m o s i adsp-21161 mosi i adsp-21161 mosi i adsp-21161 spi mosi mosi mosi - miso i/o / spi m i s o i adsp-21161 miso i adsp -21161 miso i adsp-21161 spi miso miso miso - miso / opd spictl only one slave is allowed to transmit data at any given time. lxdat7-0 [data15-0] i/o [i/o/t] link port data (link ports 0-1). for silicon revisions 1.2 and higher, each lxdat pin has a keeper latch that is enabled when used as a data pin; or a 20k ? . 0. 1.0 1.1 50 ? . l1data[7:0] are multiplexed with the data[15:8] pins l0data[7:0] are multiplexed with the data[7:0] pins. if link ports are disabled and are not be used, then these pins can be used as additional data lines for executing instructions at up to the full clock ra te from external memory. see data47:16 for more information. lxclk i/o link port clock (link ports 0-1). each lxclk pi n has an internal pull-down 50 k ? . ( 01). 50 ? . . bms t lboot i l b bms t bms i/o/t b m s s eboot lboot t h prom dma 10 epb0 l spi dma t- eprom bms t 2 p d p t
?15? rev. 0 ADSP-21161N clkin i local clock in . used in conjunction with xtal. cl kin is the ADSP-21161N clock input. it configures the ADSP-21161N to use either its internal clock ge nerator or an external clock source. connecting the necessary components to clkin and xtal enables the internal clock generator. connecting the external cloc k to clkin while leaving xtal unconnected configures the ADSP-21161N to use the external clock source such as an external clock oscillator.the ADSP-21161N external port cycles at the frequency of clkin. the instruction cycle rate is a multiple of the clki n frequency; it is programmable at power-up via the clk_cfg1-0 pins. clkin may not be halted, changed, or operated below the specified frequency. xtal o crystal oscillator terminal 2 . used in conjunction with clkin to enable the ADSP-21161N's internal clock oscillator or to di sable it to use an external clock source. see clkin. clk_cfg1-0 i core/clkin ratio control . ADSP-21161N core clock (ins truction cycle) rate is equal to n x plliclk where n is user selectable to 2, 3, or 4, using the clk_cfg1-0 inputs. these pins can also be used in combination with the clkdbl 6 x clki x clki c r r clkdbl clkdbl i c d m e t 2x clkout 1x 2x clki t clki x tal t t al x x 25 mh x clkdbl tal 50 mh pll t 2x reset clkdbl gd ddet 1x x 25 mh 100 mh 50 mh clkout cl kcg10 clkcg10 clkdbl 0 t x t 100 mh clki x tal c r r clkdbl clkcg1 clkcg0 cclki clkiclkout 10 0 21 1x 10 1 31 1x 01 0 41 1x 00 0 41 2x 00 1 61 2x 01 0 1 2x a 1 125 mh 100 mh 25 mh clkout x s 10 p 21 when using an external crystal, the maximum crystal frequency cannot exceed 25 mhz. for all other external clock sources, the maximum clkin frequency is 50 mhz. table 2. pin descriptions (continued) pin type function
?16? ADSP-21161N rev. 0 clkout o/t local clock out . clkout is 1x or 2x and is driven at either 1x or 2x the frequency of clkin frequency by the current bus master . the frequency is determined by the clkdbl t - adsp-21161 hbg a dsp clkout t adsp-21161 id2-000x i clkdbl clkout 2xclki i clkdbl clkout 1xclki clkout is only controlled by the clkdbl pin and operates at either 1xclkin or 2xclkin. do not use clkout in multiproces sing systems. use clkin instead. reset i/a p r r adsp-21161 x t reset - rstout 1 o r o w rstout i 406 reset pll tck i t c ta g p tag tms i/s t m s ta g u tms 20 ? . () . . 20 ? . () . . trst i/a t r tag r trst - adsp-21161 trst 20 ? . emu o o/d e s m adsp -21161 a d dsp t tag emu - ddit p c p s 1 dsp 14 ddet p i/o p s 33 13 a d d p a p s 1 dsp pll t ddit x p s p agd g a p s r gd g p s r 26 c d c r 5 1 rstout x 12 t 2 p d p t
?17? rev. 0 ADSP-21161N boot modes table 3. boot mode selection eboot lboot bms bm rm bms eprom 0 0 1 i h p 0 1 0 i s b spi 0 1 1 i l p 0 0 0 i b p x x 1 1 x i r
?18? ADSP-21161N rev. 0 specifications recommended operating conditions parameter 1 1 specifications subject to change without notice. c grade k grade test conditions min max min max unit v ddint internal (core) supply voltage 1.71 1.89 1.71 1.89 v av dd analog (pll) supply voltage 1.71 1.89 1.71 1.89 v v ddext external (i/o) supply voltage 3.13 3.47 3.13 3.47 v v ih high level input voltage 2 2 applies to input and bidirectio nal pins: data47 -16, addr23-0, ms 3-0 rd wr ack sbts irq 2-0 lag11-0 hbg hbr cs dmar 1 dmar 2 br 6-1 id2-0 rpba pa brst sx dxa dxb sclkx ras cas sdwe sdclk0 lxdat-0 lxclk lxack spiclk mosi miso spids eboot lboot bms sdcke clkcgx clkdbl clki reset trst tck tms tdi ddet x 20 ddet 05 20 ddet 05 il l l i 2 ddet -05 0 -05 0 t case c o t 3 3 s t c p 55 -40 105 0 5 1 1 . 2 2 16 20 ms 3-0 rd wr ack dqm lag11-0 hbg red dmag 1 dmag 2 br 6-1 bmstr pa brst sx dxa dxb sclkx ras cas sdwe sda10 lxdat-0 lxclk lxack spiclk mosi miso bms sdclkx sdcke emu tal tdo clkout timep rstout ddet i oh -20 a 3 3 s o d c p 54 24 ol l l o 2 ddet i ol 40 a 3 04 i ih h l i c 45 4 a data4-16 addr23-0 ms 3-0 sbts irq 2-0 lag11-0 hbg hbr cs br 6-1 id2-0 rpba brst sx dxa dxb sclkx ras cas sdwe sdclk0 lxdat-0 lxclk lxack spiclk mosi miso spids eboot lboot bms sdcke clkcgx clkdbl tck reset clki 5 a 20 ? rd wr ack dmar 1 dmar 2 pa trst tms tdi ddet x i ddet x 10 a i il l l i c 4 ddet x i 0 10 a i ihc clki h l i c 6 6 a clki ddet x i ddet x 25 a i ilc clki l l i c 6 ddet x i 0 25 a i ikh k h l c a addr 23-0 data4-0 ms3 -0 brst clkout ddet x i 20 250 100 a i ikl k l l c ddet x i 0 50 200 a i ikh-od k h o c c ddet x 300 a i ikl-od k l o c ddet x 300 a i ilpu l l i c p-u 5 ddet x i 0 250 a i oh t-s l c 101112 ddet x i ddet x 10 a i ol t-s l c 101314 ddet x i 0 10 a i olpu1 t-s l c p-u1 11 ddet x i 0 500 a i olpu2 t-s l c p-u2 12 ddet x i 0 250 a i ohpd1 t-s l c p-d1 13 ddet x i ddet x 250 a i ohpd2 t-s l c p-d2 14 ddet x i ddet x 500 a i dd-ipeak s c i 1516 cclk 100 ddit x 00 a i dd-ihigh s c i 161 cclk 100 ddit x 650 a i dd-ilow s c i 161 cclk 100 ddit x 500 a i dd-idle s c i 161 cclk 100 ddit x 400 a ai dd s c a 20 a dd x 10 a c i i c 2122 i 1 mh t case 25c i 1 4
?19? rev. 0 ADSP-21161N absolute maximum ratings esd sensitivity 9 characterized, but not tested. 10 applies to three-statable pi ns: data47-16, addr23-0, ms 3-0 clkout lag11-0 red hbg bms br 6-1 ras cas sdwe dqm sdclkx sdcke sda10 brst 11 a - 20 ? rd wr dmag 1 dmag 2 pa 12 a - 50 ? . emu miso mosi 13 a - 50 ? 0 ( 1.2) . 2 . 1.2 . 1 20 ? 0 ( 1.2 ). 15 . . 21. 16 . 1 . 21. 1 . 21. 1 21161 . 21. 20 . 21 . 22 . () 1 ( ) . . . 0. +2.2 () ( . . . . . . . 0. +2.2 () ( . . . . . 0. +.6 . . . . . . . . . . . . . . . . . . 0.5 + 0.5 . . . . . . . . . . . . 0.5 + 0.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 . . . . . . . . . . . . . 65 +150 1 . . . ( ) . 000 . 21161 . .
?20? ADSP-21161N rev. 0 timing specifications the ADSP-21161N?s internal clock switches at higher frequen- cies than the system input clock (clkin). to generate the internal clock, the dsp uses an internal phase-locked loop (pll). this pll-based clocking minimizes the skew between the system clock (clkin) signal and the dsp?s internal clock (the clock source for the external port logic and i/o pads). the ADSP-21161N?s internal clock (a multiple of clkin) provides the clock signal for timing internal memory, processor core, link ports, serial ports, and external port (as required for read/write strobes in asynchronous access mode). during reset, program the ratio between the dsp?s internal clock frequency and external (clkin) clock frequency with the clk_cfg1-0 and clkdbl e x c r r clkdbl clkdbl t 2 p 11 t dix lxclkd clki 10 c--clki 21 31 41 61 1 x i clkout--clki 11 21 t 4 clkout cclk c g o t r d c clki i c 1/ ck clkout ex p s c 1/ tckop plliclk pll i c 1/ plli cclk c c 1/ cclk t r d 1 ck clki c p cclk p c c p lclk l p c p cclk ( ) ( ) ( ) 1 (1 2 1 ) ( ) (11 12 ) ( )
?21? rev. 0 ADSP-21161N use the exact timing information gi ven. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect sta- tistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 39 on page 54 under test conditions for voltage reference levels. switching characteristics specify how the processor changes its signals. circuitry external to th e processor must be designed for compatibility with these signal characteristics. switching charac- teristics describe what the processor will do in a given circumstance. use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. during reset, the dsp will not respond to sbts hbr mms a dsp hbr hbg dsp dsp power dissipation total power dissipation has two components: one due to internal circuitry and one due to the switching of external output drivers. internal power dissipation depends on the instruction execution sequence and the data operands in volved. using the current spec- ifications (i ddinpeak , i ddinhigh , i ddinlow , i ddidle ) from the electrical characteristics on page 18 and the current-ver- sus-operation information in table 5 , the programmer can estimate the ADSP-21161N?s internal power supply (v ddint ) input current for a specific applicat ion, according to the following formula: figure 10. core clo ck and system clock re lationship to clkin cl k in clkdbl clkout input clock doubler 1: 1, 2:1 2:1, 3:1, 4:1 cclk core clock ti e t o gn d t o enable 2x ope ratio n plliclk crystal or clock oscillator clk_cfg[1:0] xtal p ll e xterna l port sd ram x1, x1 /2 if bus master sdclk[1:0] ex te rnal p ort h ost, mms, sram, sbram x1, x1 /2 % peak i ddinpeak % high i ddinhigh % low i ddinlow + % idle i ddidle i ddint --------------------------------------------------
?22? ADSP-21161N rev. 0 the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: ? () ? () ? () ? ( ) 2 f the load capacitance should include the processor package capacitance (c in ). the switching frequenc y includes driving the l o a d h i g h a n d t h e n b a c k l ow. a d d r ess and data pins can drive high and low at a maximum rate of 1/tck while writing to a sdram memory. example: estimate p ext with the following assumptions: ? (2 ) ? 1 16 10 ( ) ? 1 50 ? 50 ? 100 ? ? 6 . 6 . 1. 21 . 1. 1 . . 100 . 100 50 . 5. 1 ( ) 1 ( ) 1 ( ) 2 2 ( 6 6) 1 ( 6) 1 2 1 2 1 ( 2) 1 ( 2) 1 ( ) . 2 21 . ( ) 20 . 6. (. ) 2 11 20 2. 50 10. 0.00 ms x 4 0 24 / 10 0000 w sdwe 1 0 24 / 10 0000 w d 32 50 14 50 mh 10 012 w sdclk0 1 100 24 100 mh 10 002 w p et 015 w p total p ext p int p ll ++ =
?23? rev. 0 ADSP-21161N power-up sequencing the timing requirements for dsp startup for silicon revision 0.3, 1.0, or 1.1 are given in table 7 . table 7. power-up sequencing ti ming requirements (dsp startup) name parameter min max unit timing requirements t rstvdd reset ddit / ddet 0 ddramp ddit / ddet 1 1 t 0 / - 2 ddit 0 1 36 ddet 0 33 0000 / iddedd ddit ddet 50 200 clkdd clki ddit / ddet 0 200 ddrst ddit / ddet reset 2 2 t 0 ddit ddet t ddit ddet 1 33 reset 0 clkrst clki reset 3 3 t 100 clki - - r - a 25 x - tal x 100 pll clki 100 pllrst pll reset 20 figure 11. power-up sequencing for revisions 0.3, 1.0, and 1.1 reset clkdbl clkcg-0 clki rstdd ddet ddit clkrst ddramp iddedd ddramp pllrst clkdd ddrst
ADSP-21161N ?24? rev. 0 the timing requirements for dsp startup fo r silicon with revision 1.2 are given in table 8 . rstout x adsp-21161 03 10 11 t - b15 d - dsp - i/o esd t esd a d s t s 1 33 13 i adsp-21161 33 i s esd w 1 33 s 33 1 t p-u s t r dsp s p m mx u timing requirements t rstvdd reset ddit / ddet 0 iddedd ddit ddet 50 200 clkdd clki ddit / ddet 12 1 ddit / ddet 1 33 2 clki - x 0 200 clkrst clki reset 3 3 a clki - - r - a 25 x - tal x 10 pllrst pll reset 4 4 b clki tbd wrst s reset 5 5 a - s 4 clki reset i/o 4 ck switching requirements t corerst dsp core reset deasserted after reset 406 ck 46 6 t 406 srst t 10 i 1 clki 40 x figure 12. power-up sequ encing for revision 1.2 reset rstout clkdbl clk_cfg1-0 clkin t rstvdd vddext vddint t pllrst t clkrst t clkvdd t ivddevdd t corerst
?25? rev. 0 ADSP-21161N clock input clkin must be used as the clock source for sbsram. an extern al crystal cannot be used when interfacing with sbsram. do not use clkout as the clock source for the sbsram de vice. using an external crystal in conjunction with clkdbl clkout clki clkout clock signals the ADSP-21161N can use an external clock or a crystal. se e clkin pin description. the programmer can configure the ADSP-21161N to use its internal clock generator by co nnecting the necessary compon ents to clkin and xtal. figure 15 shows the component connections used for a cr ystal operating in fundamental mode. figure 13. dual vo ltage schottky diode table 9. clock input parameter 100 mhz unit min max timing requirements t ck clkin period 20 60 ns t ckl clkin width low 7.5 30 ns t ckh clkin width high 7.5 30 ns t ckrf clkin rise/fall (0.4 v-2.0 v) 3 ns figure 14. clock input figure 15. 100 mhz operation (fundamental mode crystal) 3.3v i/o voltage regulator 1.8v core voltage regulator v ddext v ddint ADSP-21161N dc input source clkin t ckh t ck t ckl clkin xtal c1 c2 27pf 27pf x1 suggested components for 100 mhz operation: ecliptek ec2sm-25.000m (surface mount package) ecliptek ec-25.000m (through-hole package) c1 = 27 pf c2 = 27 pf note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. this 25 mhz crystal generates a 100 mhz cclk and a 50 mhz ep clock with clkdbl eabled ad a 2 pll multipl rati
ADSP-21161N ?26? rev. 0 reset table 10. reset parameter min max unit timing requirements t wrst reset p l 1 1 a - a - - 100 reset dd clki - x 4 ck srst reset s b clki h 2 2 o adsp-211 61 clki pc adsp-21161 x 5 figure 16. reset clkin reset wrst srst
?27? rev. 0 ADSP-21161N interrupts timer table 11. interrupts parameter min max unit timing requirements t sir irq2-0 s b clki h 1 1 o irqx 6 hir irq2-0 h a clki h 1 0 ipw irq2-0 p 2 2 a sir hir 2 ck figure 17. interrupts table 12. timer parameter min max unit switching characteristic t dtex clkin high to timexp17ns figure 18. timer clkin irq2-0 ipw sir hir clki timep dte dte
ADSP-21161N ?28? rev. 0 flags table 13. flags parameter min max unit timing requirement t sfi flag11-0in setup before clkin high 1 1 flag inputs meeting these setup and hold times for instruction cycle n will affect conditional instructions in instruction cycl e n+2. 4ns t hfi flag11-0in hold after clkin high 1 1ns t dwrfi flag11-0in delay after rd / wr l 1 12 hiwr lag11-0i h a rd / wr d 1 0 switching characteristics t dfo flag11-0out delay after clkin high 9 ns t hfo flag11-0out hold after clkin high 1 ns t dfoe clkin high to flag11-0out enable 1 ns t dfod clkin high to flag11-0out disable 5 ns figure 19. flags clkin flag11-0 out flag output clkin rd wr lag iput lag-0 i d h d dd de si hi hiwr dwri
?29? rev. 0 ADSP-21161N memory read ? bus master use these specifications for asynchronous in terfacing to memories (and memory-mapped pe ripherals) without reference to clkin. these specifications apply when the adsp-211 61n is the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rd wr dmag t 14 m r b m p m mx u timing requirements : t dad address, selects de lay to data valid 1,2 1 data delay/setup: user must meet t dad , t drld , or t sds. 2 the falling edge of ms x bms ck 025 cclk 11w drld rd l d 13 3 ack data rd wr dmag 05 ck 11w hda d h a s 4 4 d h u hda hdrh s ex s h t c p 54 0 sds d s rd h hdrh d h rd h 34 1 daak ack d a s 25 5 ack d/s u daak dsak sakc ack l ack h ck 05 cclk 12w dsak ack d rd l 35 ck 05 cclk 11w sakc ack s clki 35 05 cclk 3 hakc ack h a clki 3 1 switching characteristics t drha address selects hold after rd h 3 025 cclk 1h darl a s rd l 2 025 cclk 3 rw rd p 3 ck 05 cclk 1w rwr rd h wr rd dmagx l 3 05 cclk 1hi w wait ck hi ck wait hi 0 h ck wait h 0 figure 20. memory read ? bus master wr dmag ack data rd address ms bms darl rw dad daak hdrh hda rwr drld drha dsak sds sakc hakc clki
ADSP-21161N ?30? rev. 0 memory write ? bus master use these specifications for asynchronous in terfacing to memories (and memory-mapped pe ripherals) without reference to clkin. these specifications apply when the adsp-211 61n is the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rd wr dmag t 15 m w b m p m mx u timing requirements: t daak ack delay from address, selects 1,2 1 ack delay/setup: user must meet t daak or t dsak or t sakc for deassertion of ack (low); all three specifications must be met for assertion of ack (high). 2 the falling edge of msx bms ck 05 cclk 12w dsak ack d wr l 13 3 ack data rd wr dmag ck 05 cclk 11w sakc ack s clki 13 05 cclk 3 hakc ack h a clki 13 1 switching characteristics: t dawh address, selects to wr d 23 ck 025 cclk 3w dawl a s wr l 2 025 cclk 3 ww wr p 3 ck 05 cclk 1w ddwh d s wr h 3 ck 025 cclk 125w dwha a h wr d 3 025 cclk 1h dwhd d h wr d 3 025 cclk 1h datrwh d d wr d 34 4 s ex s h t c p 54 025 cclk 2h 025 cclk 25h wwr wr h wr rd dmagx l 3 05 cclk 125hi ddwr d d wr rd l 025 cclk 3i wde wr l d e 025 cclk 1 w wait ck h ck wait h 0 hi ck wait hi 0 i ck wait i 0 figure 21. memory write ? bus master t datrwh rd dmag ack data wr address ms bms dawl ww daak wwr wde ddwr dwha dawh dsak ddwh dwhd sakc hakc clki
?31? rev. 0 ADSP-21161N synchronous read/write ? bus master use these specifications for interfacing to external memory system s that require clkin, relative to timing or for accessing a s lave ADSP-21161N (in multiprocessor memory space). these synchronous sw itching characteristics are also valid during asynchronous memory reads and writes except where noted (see memory read ? bus master on page 29 and synchronous read/write ? bus master on page 31 ). when accessing a slave ADSP-21161N, these switching charac teristics must meet the slave's timing requirements for synchronous read/writes (see synchronous read/write ? bus slave on page 33 ). the slave ADSP-21161N must also meet these (bus master) timing requirements for data and acknowledge setup and hold times. table 16. synchronous read/write ? bus master parameter min max unit timing requirements t ssdati data setup before clkin 1 1 note that timing for ack, data, rd wr dmag 55 hsdati d h a clki 1 1 sackc ack s b clki 1 05 cclk 3 hackc ack h a clki 1 1 switching characteristics t daddo address, ms x bms brst d a clki 10 haddo a ms x bms brst h a clki 15 drdo rd h d a clki 1 025 cclk 1 025 cclk dwro wr h d a clki 1 025 cclk 1 025 cclk drwl rd / wr l d a clki 025 cclk 1 025 cclk ddato d d a clki 125 hdato d h a clki 15 dckoo clkout d a clki 0 2 ckop clkout p 2 2 a dsp clkout - s d adsp-21160 adsp-21161 sharc ds p t r ck -1 ck 1 ckwh clkout w h 2 ck /2 - 2 ck /2 2 ckwl clkout w l 2 ck /2 - 2 ck /2 2
ADSP-21161N ?32? rev. 0 figure 22. synchronous read/write ? bus master clkin clkout address msx, brst ack (in) rd data ut wr data i write ccle read ccle drwl hsdati ssdati drd dwr hdat ddat drwl sackc hackc dck ckp ckwl hadd dadd ckwh
?33? rev. 0 ADSP-21161N synchronous read/write ? bus slave use these specifications for ADSP-21161N bus master accesses of a slave's iop registers in multip rocessor memory space. the bus master must meet these (bus slave) timing requirements. table 17. synchronous read/write ? bus slave parameter min max unit timing requirements : t saddi address, brst setup before clkin 5 ns t haddi address, brst hold after clkin 1 ns t srwi rd / wr s b clki 5 hrwi rd / wr h a clki 1 ssdati d s b clki 55 hsdati d h a clki 1 switching characteristics t ddato data delay after clkin 12.5 ns t hdato data hold after clkin 1.5 ns t dackc ack delay after clkin 10 ns t hacko ack hold after clkin 1.5 ns figure 23. synchronous read/write ? bus slave clkin address ack data (out) write access data (in) read access t saddi t haddi t dackc t hacko t hrwi t srwi t ddato t hdato t srwi t hrwi t hsdati t ssdati rd wr
ADSP-21161N ?34? rev. 0 multiprocessor bus request and host bus request use these specifications for passing of bus ma stership between multiprocessing ADSP-21161Ns ( brx hbr hbg asynchronous read/write ? host to ADSP-21161N use these specifications for asynchronous host processor a ccesses of an ADSP-21161N, after the host has asserted cs hbr a hbg adsp-21161 rd wr adsp-21161 iop hbr hbg host internal memory access is not supported. table 18. multiprocessor bus request and host bus request parameter min max unit timing requirements: t hbgrcsv hbg l rd / wr / cs 1 shbri hbr s b clki 1 1 o 6 hhbri hbr h a clki 1 1 shbgi hbg s b clki 6 hhbgi hbg h a clki h 1 sbri br x s b clki hbri br x h a clki h 05 spai pa s b clki hpai pa h a clki h 1 srpbai rpba s b clki 6 hrpbai rpba h a clki 2 switching characteristics t dhbgo hbg d a clki hhbgo hbg h a clki 15 dbro br x d a clki hbro br x h a clki 10 dpaso pa d a clki s trpas pa d a clki s 15 dpamo pa d a clki m 025 cclk patr pa d b clki m 025 cclk -5 drdcs red o/d a/d l cs hbr l 2 2 o/d a/d 05 ck trdhg red o/d d red a/d h hbg 2 34 ardtr red a/d d cs hbr h 2 11
?35? rev. 0 ADSP-21161N figure 24. multiprocessor bus request and host bus request brx i hbri hb r cs rp ba re d d re d ad hb g u t rd wr cs d pe drai ad actie drie hr p b ai srpbai drdcs hbgrcs trdhg ardtr sh b gi hhbgi sb r i clki hb r hb g u t pa ut s la e hhbri sh b r i hhbg dhbg dbr hbr dp a s trpas pa ut master dpam patr pa i d hpai spai br xut hb g i
ADSP-21161N ?36? rev. 0 table 19. read cycle parameter min max unit timing requirements t sadrdl address setup cs l b rd l 0 hadrdh a h cs h l a rd 2 wrwh rd / wr h w 35 drdhrd rd h d a red o/d d 0 drdhrd rd h d a red a/d d 0 switching characteristics t sdatrdy data valid before redy disable from low 2 ns t drdyrdl redy (o/d) or (a/d) low delay after rd l 10 rdprd red o/d a/d l p r ck - 3 hdarwh d d a rd h 26 t 20 w c p m mx u timing requirements t scswrl cs l s b wr l 0 hcswrh cs l h a wr h 0 sadwrh a s b wr h 6 hadwrh a h a wr h 2 wwrl wr l w cclk +1 rd / wr h w 35 dwrhrd wr h d a red o/d a/d d 0 sdatwh d s b wr h 5 hdatwh d h a wr h 4 switching characteristics t drdywrl redy (o/d) or (a/d) low delay after wr / cs l 11 rdpwr red o/d a/d l p w 12
?37? rev. 0 ADSP-21161N figure 25. asynchro nous read/write ? host to ADSP-21161N redy (o/d) rd read cycle address/cs data (out) redy (a/d) o/d = open drain, a/d = active drive redy (o/d) wr write cycle data (in) address redy (a/d) cs t drdyrdl t hdarwh t rdyprd t drdhrdy t sd a tr dy t sdatwh t hdatwh t drdywrl t hadwrh t rdypwr t dwrhrdy t sa d wr h t scswrl t hcswrh t hadrdh t wrw h t wwrl t wrwh t sa d r dl
ADSP-21161N ?38? rev. 0 three-state timing ? bus master, bus slave, hbr, sbts these specifications show how the memory inte rface is disabled (stops driving) or enab led (resumes driving) relative to clkin a nd the sbts t b tc h t c sbts t 21 t-s t b s hbr sbts m m timing requirements t stsck sbts s b clki 6 htsck sbts h a clki 2 switching characteristics t miena address/select enable after clkin 1.5 9 ns t miens strobes enable after clkin 1 1 strobes = rd wr dmag x ? 1.5 hbg e a clki 15 mitra a/s d a clki -025 cclk ?6 ? 0.25 0.25 .5 0.25 hbg d a clki ? .5 2 2 2 . 1.5 10 2 1.5 6 2 1.5 0.5 5 15 20 ?5 hbg l 3 3 m i a rd wr msx dmag x bms eprom 15 ck 4 15 ck 2 strhbg rd / wr / dmagx d b hbg l3 ck 0.25 ? + 0.25 +2 bms d b hbg l3 05 ck 4 05 ck 2 mehbg m i e a hbg h 3 ck 5 ck 5
?39? rev. 0 ADSP-21161N figure 26. thre e-state timing clkin sbts ack memory interface hbg memory interface = address, rd, wr, msx, hbg, dmagx. bms (in eprom boot mode) clkout t cdctr data memory interface t mitra, t mitrs, t mitrhg t htsck t cdcen t miena, t miens, t mienhg clkin t atrhbg, t strhbg, t btrhbg t stsck t daten t acken t dattr t acktr t menhbg
ADSP-21161N ?40? rev. 0 dma handshake these specifications describe the three dm a handshake modes. in all three modes dmar dmag x x addr23-0 rd wr ms 3-0 ack dmag p m addr23-0 rd wr ms 3-0 ack dmag p m m r -b m m w-b m s r/w-b m addr23-0 rd wr ms 3-0 data4-16 ack t 22 dma h p m mx u timing requirements: t sdrc dmarx s b clki 1 1 o 35 wdr dmarx w l 2 2 mx dmarx/dmagx wdr dmarh cclk 45 cclk 452 345 mh t - cclk 45 sdatdgl d s a dmagx l 3 3 sdatdgl dmarx o dmarx datdrh dmarx ck 05 cclk hdatidg d h a dmagx h 2 datdrh d a dmarx h 3 ck 3 dmarll dmarx l e l e 4 4 u dmarll dmarx clki o wdr dmarh ck dmarh dmarx w h 2 cclk 45 switching characteristics: t ddgl dmagx l d a clki 025 cclk 1 025 cclk wdgh dmagx h w 05 cclk 1hi wdgl dmagx l w ck 05 cclk 1 hdgc dmagx h d a clki ck 025 cclk 10 ck 025 cclk datdgh d b dmagx h 5 5 datdgh dmarx i dmarx datdgh ck 25 cclk ck x ck 025 cclk ck 025 cclk 5 datrdgh d d a dmagx h 6 6 s ex s h t c p 54 025 cclk 3 025 cclk 30 dgwrl wrx l b dmagx l 15 2 dgwrh dmagx l b wrx h ck 05 cclk 2w dgwrr wrx h b dmagx h t 15 2 dgrdl rdx l b dmagx l 15 2 drdgh rdx l b dmagx h ck 05 cclk 2w dgrdr rdx h b dmagx h 15 2 dgwr dmagx h wrx rdx dmagx l 05 cclk 2hi dadgh a/s dmagx h 15 ddgha a/s h dmagx h 1 w wait . ( 0).
?41? rev. 0 ADSP-21161N figure 27. dma handshake timing clkin t sdrc dmar data data rd wr wdr sdrc dmarh dmarll hdgc wdgh ddgl dmag datdgh datdrh datrdgh hdatidg dgwrl dgwrh dgwrr dgrdl drdgh dgrdr sdatdgl memr read bus master memr write bus master r schrus readwrite bus master timig speciicatis r addr 2-0 rd wr ms -0 ad ack als appl here eteral deice t eteral memr eteral memr t eteral deice trasers betwee adsp-2 iteral memr ad eteral deice trasers betwee eteral deice ad eteral memr eteral hadshake mde ddgha address ms dadgh wdgl rm eteral drie t adsp-2 rm adsp-2 t eteral drie
ADSP-21161N ?42? rev. 0 sdram interface ? bus master use these specifications for ADSP-21161N bus master accesses of sdram: sdram interface ? bus slave these timing requirements allow a bus slave to sample the bu s master?s sdram command and detect when a refresh occurs: table 23. sdram interface - bus master parameter min max unit timing requirements : t sdsdk data setup before sdclk 2.0 ns t hdsdk data hold after sdclk 1.5 ns switching characteristics : t dsdk1 first sdclk rise delay after clkin 1,2 1 for the second, third, and fourth rising edges of sdclk delay from clkin, add approp riate number of sdclk period to the t dsdk1 and t ssdkc1 values, depending upon the sdckr value and the core clock to clkin ratio. 2 subtract t cclk from result if value is greater than or equal to t cclk . 0.75t cclk + 1.5 0.75t cclk + 8.0 ns t sdk sdclk period t cclk 2 x t cclk ns t sdkh sdclk width high 3 3 sdckr = 1 for sdclk equal to core clock frequency and sdckr = 2 for sdclk equal to half core clock frequency. 4 ns t sdkl sdclk width low 4 ns t dcadskd command, address, data, delay after sdclk 4 4 command = sdcke, msx dqm ras cas sda10 sdwe 025 cclk 25 hcadsdk c a d h sdclk 4 13 sdtrsdk d t-s sdclk 5 5 sdram c sdram clk - 05 cclk 20 sdesdk d e a sdclk 05 cclk sdctr c t-s a clki 05 cclk 10 05 cclk 60 sdce c e a clki 2 5 sdsdktr sdclk t-s clki 0 3 sdsdke sdclk e clki 1 4 sdatr a t-s clki ? 0.25 ? 5 ? 0.25 0. .2 2. timing requirements : t ssdkc1 first sdclk rise after clkout 1,2,3 1 for the second, third, and fourth rising edges of sdclk delay from clkout, add appropriate number of sdclk period to the t dsdk1 and t ssdkc1 values, depending upon the sdckr value and the core clock to clkout ratio. 2 sdckr = 1 for sdclk equal to core clock frequency and sdckr = 2 for sdclk equal to half core clock frequency. 3 subtract t cclk from result if value is greater than or equal to t cclk . sdckr x t cclk ? 0.5 ? 0.5 ? 0.25 + 2.0 msx dqm ras cas sda10 sdwe 2 hcsdk c h sdclk 4 1
?43? rev. 0 ADSP-21161N figure 28. sdram interface clkin sdclk data(in) data(out) cmnd 1 addr (out) cmnd 1 (out) addr (out) clkout sdclk (in) cmnd 2 (in) t dsdk2 t sdk t dsdk1 t sdkh t sdkl t sdsdk t thdsdk t dcadsdk t sdensdk t sdtrsdk t hcadsdk t dcadsdk t hcadsdk t sdcen t sdctr t sdatr t sdaen t ssdkc2 t ssdkc1 t scsdk t hcsdk notes 1. command = sdcke, msx, ras, cas, sdwe, dqm and sda10. 2. sdram controller adds one sdram clock three-stated c y cle dela y onareadfollowedb y awrite.
ADSP-21161N ?44? rev. 0 link ports calculation of link receiver data setup and hold relative to lin k clock is required to determine the maximum allowable skew tha t can be introduced in the transmission path between ldata and lclk . setup skew is the maximum delay that can be introduced in ldata relative to lclk, (setup skew = t lclktwh min ? t dldch ? t sldcl ). hold skew is the maximum delay that can be introduced in lclk relative to ldata, (hold skew = t lclktwl min ? t hldch ? t hldcl ). calculations made directly from speed specifications will result in unrealistically small skew times because they include mu ltiple tester guardbands. the setup and hold skew times shown below are calculated to include only one tester guardband. ADSP-21161N setup skew = 1.5 ns max ADSP-21161N hold skew = 1.5 ns max note that there is a two-cycle effect latency between the lin k port enable instruction and the dsp enabling the link port. table 25. link ports receive parameter min max unit timing requirements t sldcl data setup before lclk low 1 ns t hldcl data hold after lclk low 3.5 ns t lclkiw lclk period t lclk ns t lclkrwl lclk width low 4.0 ns t lclkrwh lclk width high 4.0 ns switching characteristics t dlalc lack low delay after lclk high 1 1 lack goes low with t dlalc relative to rise of lclk after first nibble, but does not go low if the receiver's link buffer is not about to fill. 812ns figure 29. link ports?receive lclk ldat(7:0) lack (out) receive in t sldcl t hldcl t dlalc t lclkrwl t lclkiw t lclkrwh
?45? rev. 0 ADSP-21161N table 26. link ports transmit parameter min max unit timing requirements t slach lack setup before lclk high 8 ns t hlach lack hold after lclk high ?2 ns switching characteristics t dldch data delay after lclk high 3 ns t hldch data hold after lclk high 0 ns t lclktwl lclk width low .5t lclk ?1.0 .5t lclk +1.0 ns t lclktwh lclk width high .5t lclk ?1.0 .5t lclk +1.0 ns t dlaclk lclk low delay after lack high .5t lclk +3 3t lclk +11 ns figure 30. link ports?transmit lclk ldat(7:0) lack (in) the t slach requirement applies to the rising edge of lclk only for the first nibble transmitted. transmit last nibble/byte transmitted first nibble/byte transmitted lclk inactive (high) out t dldch t hldch t lclktwh t lclktwl t slach t hlach t dlaclk
ADSP-21161N ?46? rev. 0 serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confi rmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width. table 27. serial ports - external clock parameter min max unit timing requirements t sfse transmit/receive fs setup before transmit/receive sclk 1 1 referenced to sample edge. 3.5 ns t hfse transmit/receive fs hold after transmit/receive sclk 1, 2 2 fsx hold after receive sclk when mce = 1, mfd = 0 is 0 ns minimum from drive edge. transmit fs hold after transmit sclk for lat e external transmit fs is 0 ns minimum from drive edge. 4ns t sdre receive data setup before receive sclk 1, 3 3 sclk/fs configured as a receive clock/frame sy nc with the ddir bit = 0 in spctlx register. 1.5 ns t hdre receive data hold after sclk 1, 4 4 sclk/fs configured as a transmit clock/frame sy nc with the ddir bit = 1 in spctlx register. 4ns t sclkw sclkx width 7 ns t sclk sclkx period 2t cclk ns table 28. serial ports - internal clock parameter min max unit timing requirements t sfsi fs setup time before sclk 1, 2 1 referenced to sample edge. 2 sclk/fs configured as a receive clock/frame sy nc with the ddir bit = 0 in spctlx register. 8ns t hfsi fs hold after sclk 1,2,3 3 fsx hold after receive sclk when mce = 1, mfd = 0 is 0 ns minimum from drive edge. transmit fs hold after transmit sclk for lat e external transmit fs is 0 ns minimum from drive edge. 0.5t cclk +1 ns t sdri receive data setup before sclk 1 4ns t hdri receive data hold after sclk 1 3ns table 29. serial ports - ex ternal or internal clock parameter min max unit switching characteristics t dfse fs delay after sclk 1 (internally generated fs) 2 1 sclk/fs configured as a receive clock/frame sy nc with the ddir bit = 0 in spctlx register. 2 referenced to drive edge. 13 ns t hofse fs hold after sclk (internally generated fs) 1 3ns table 30. serial ports - external clock parameter min max unit switching characteristics t dfse fs delay after sclk (internally generated fs) 1,2 1 referenced to drive edge. 2 sclk/fs configured as a transmit clock/frame sy nc with the ddir bit = 1 in spctlx register. 13 ns t hofse fs hold after sclk (internally generated fs) 1,2 3ns t ddte data delay after slck 1,2 16 ns t hdte data hold after sclk 1,2 0ns
?47? rev. 0 ADSP-21161N table 31. serial ports - internal clock parameter min max unit switching characteristics t dfsi fs delay after sclk (internally generated fs) 1, 2 4.5 ns t hofsi fs hold after sclk (internally generated fs) 1,2 -1.5 ns t ddti data delay after sclk 1,2 7.5 ns t hdti data hold after sclk 1,2 0ns t sclkiw sclk width 2 .5t sclk ?2.5 .5t sclk +2 ns 1 referenced to drive edge. 2 sclk/fs configured as a transmit clock/frame sync with the ddir bit = 1 in spctlx register. table 32. serial ports - enable and three-state parameter min max unit switching characteristics t ddten data enable from external transmit sclk 1,2 4ns t ddtte data disable from external transmit sclk 1 10 ns t ddtin data enable from internal transmit sclk 1 0ns t ddtti data disable from internal transmit sclk 1 3ns 1 referenced to drive edge. 2 sclk/fs configured as a transmit clock/frame sync with the ddir bit = 1 in spctlx register. table 33. serial ports - external late frame sync parameter min max unit switching characteristics t ddtlfse data delay from late external transmit fs or external receive fs with mce = 1, mfd = 0 1 13 ns t ddtenfs data enable from late fs or mce = 1, mfd = 01 0.5 ns 1 mce = 1, transmit fs enable and transmit fs valid follow t ddtlfse and t ddtenfs .
ADSP-21161N ?48? rev. 0 figure 31. serial ports drive edge sclk (int) drive edge sclk drive edge drive edge sclk sclk (ext) t ddtte t ddten t ddtti t ddtin dxa/dxb dxa/dxb sclk fs drive edge sample edge data receive? internal clock data receive? external clock sclk fs drive edge sample edge note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t sdri t hdri t sfsi t hfsi t dfsi t hofsi t sclkiw t sdre t hdre t sfse t hfse t dfse t sclkw t hofse d x a/d x b d x a/d x b t ddti sclk fs drive edge sample edge data transmit ? internal clock t sfsi t hfsi t dfsi t hofsi t sclkiw d x a/d x b t hdti note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t ddte sclk fs drive edge sample edge data transmit ? external clock t sfse t hfse t dfse t hofse t sclkw d x a/d x b t hdte
?49? rev. 0 ADSP-21161N figure 32. external late frame sync (see note 2) drive sample drive sclk fs d x a/d x b drive sample drive late external transmit fs external receive fs with mce = 1, mfd = 0 1st bit 2nd bit sclk fs 1st bit 2nd bit (see note 2) t hofse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i t hofse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i d x a/d x b
ADSP-21161N ?50? rev. 0 spi interface specifications table 34. spi interface protocol - mast er switching and timing specifications name parameter min max unit timing requirements t sspidm data input valid to spiclk edge (data input set-up time) 0.5t cclk +10 ns t hspidm spiclk last sampling edge to data input not valid 0.5t cclk +1 ns t spitdm sequential transfer delay 2t cclk ns switching characteristics t spiclkm serial clock cycle 8 t cclk ns t spichm serial clock high period 4t cclk -4 ns t spiclm serial clock low period 4t cclk -4 ns t ddspidm spiclk edge to data out valid (data out delay time) 3 t hdspidm spiclk edge to data out not valid (data out hold time) 0 t sdscim_0 flag3-0 (spi device select) low to first spiclk edge for cphase = 0 5t cclk ns t sdscim_1 flag3-0 (spi device select) low to first spiclk edge for cphase = 1 3t cclk ns t hdsm last spiclk edge to flag3-0 high t cclk -3 ns table 35. spi interface protocol - slav e switching and timing specifications name parameter min max unit timing requirements t spiclks serial clock cycle 8t cclk ns t spichs serial clock high period 4t cclk -4 ns t spicls serial clock low period 4t cclk -4 ns t sdsco spids spiclk cphase 0 cphase 1 35 cclk 15 cclk hds l spiclk spids cphase 0 0 sspids d spiclk - 0 hspids spiclk cclk 1 sdppw spids cphase0 cclk switching characteristics t dsoe spids 2 05 cclk 55 dsdhi i 2 05 cclk 55 ddspids spiclk 05 cclk 3 hdspids 1 1 w cphase 0 1 hdlsbs spiclk 025 cclk 3 hdlsbs 1 spiclk lsb 05 spiclk 45 cclk dso 2 2 a spids spids cphase0 15 cclk
?51? rev. 0 ADSP-21161N figure 33. spi master timing t sspidm t hspidm t hdspidm lsb msb t hsspidm t ddspidm mosi (output) miso (input) flag3-0 (output) spiclk (cp = 0) (output) spiclk (cp = 1) (output) t spichm t spiclm t spiclm t spiclkm t spichm t hdsm t spitdm t hdspidm lsb valid lsb msb msb valid t hspidm t ddspidm mosi (output) miso (input) t sspidm cphase=1 cphase=0 msb valid t sdscim t sspidm lsb valid
ADSP-21161N ?52? rev. 0 figure 34. spi slave timing t hspids t ddspids t dsdhi lsb msb msb valid t hspids t dsoe t ddspids t hdspids miso (output) mosi (input) t sspids spids (input) spiclk (cpol = 0) (input) spiclk (cpol = 1) (input) t sdsco t spichs t spicls t spicls t spiclks t hds t spichs t sspids t hspids t dsdhi lsb valid msb msb valid t dsoe t ddspids miso (output) mosi (input) t sspids lsb valid lsb cpha=1 cpha=0 t sdppw t dsov t hdlsbs
?53? rev. 0 ADSP-21161N jtag test access port and emulation table 36. jtag test access port and emulation parameter min max unit timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys system inputs setup before tck low 1 1 system inputs = da ta47-16, addr23-0, rd wr ack rpba spids eboot lboot dmar 2-1 clkcg1-0 clkdbl cs hbr sbts id2-0 irq 2-0 reset bms miso mosi spiclk dxa dxb sclk x sx lxdat-0 lxclk lxack sdwe hbg ras cas sdclk0 sdcke brst br 6-1 pa ms 3-0 lag11-0 2 hss s i h a tck l 1 15 trstw trst p 4 ck switching characteristics t dtdo tdo delay from tck low 13 ns t dsys system outputs delay after tck low 2 2 system outputs = bms miso mosi spiclk dxa dxb sclkx s x lxdat-0 lxclk lxack data4-16 sdwe ack hbg ras cas sdclk1-0 sdcke brst rd wr br 6-1 pa ms 3-0 addr23-0 lag11-0 dmag 2-1 dqm red clkout sda10 timep emu bmstr rstout 30 figure 35. ieee 11499.1 jtag test access port tck tms tdi tdo system inputs system outputs t stap t tck t htap t dtdo t ssys t hsys t dsys
?54? ADSP-21161N rev. 0 output drive currents figure 36 shows typical i-v characteri stics for the output drivers of the ADSP-21161N. the curves represent the current drive capability of the output drivers as a function of output voltage. test conditions output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram ( figure 37 ). if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. output disable time output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ? . . ? . ? 0.5 . example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose ? 21161 . ? 0. . ( ) ( ). (.. ). figure 36. typical drive currents source (v ddext )voltage?v 60 -10 -40 03.5 0.5 1 1.5 2 2.5 3 50 0 -20 -30 30 10 40 20 -50 -60 l o a d ( v d d e x t ) c u r r e n t ? m a v ddext =3.47v,-40c v ddext =3.3v,+25c v ddext = 3.13v, +105c v ddext = 3.13v, +105c v ddext = 3.47v, -40c v ddext =3.3v,+25c 80 -80 t decay c l ? v () i l -------------------- - = figure 37. output enable/disable figure 38. equivalent device loading for ac measurements (inclu des all fixtures) figure 39. voltage re ference levels for ac measurements (except output enable/disable) reference signal t dis output starts driving v oh (measured) -  v v ol (measured) +  v t measured v oh (measured) v ol (measured) 2.0v 1.0v v oh (measured) v ol (measured) high-impedance state. test conditions cause this voltagetobeapproximately1.5v. output stops driving t ena t decay 1.5v 30pf to output pin 50 v input or output 1.5v 1.5v
?55? rev. 0 ADSP-21161N capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 38 on page 54 ). figure 40 shows graphically how output delays and holds vary with load capaci- tance. (note that this graph or de rating does not apply to output disable delays; see output disable time on page 54 .) the graphs of figure 40 , figure 41 , and figure 42 may not be linear outside the ranges shown for typical outp ut delay vs. load capacitance and typical output rise time (20% ? 80%, v = min) vs. load capacitance. environmental conditions thermal characteristics the ADSP-21161N is packaged in a 225-lead mini ball grid array (mbga). the ADSP-21161N is specified for a case tem- perature (tcase). to ensure that the tcase data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. use the center block of ground pins (mbga balls: f6-10, g6-10, h6-10, j6-10, k6-10) to provide thermal pathways to the printed circuit board?s ground plane. a heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive. where: ? t case = case temperature (measured on top surface of package) ? pd = power dissipation in w (this value depends upon the specific application; a me thod for calculating pd is shown under power dissipation). ? . ? jb = 8.0 c/w figure 40. typical output delay or hold vs. load capacitance (at max case temperature) figure 41. typical output rise/fall time (20% ? 80%, v ddext = max) figure 42. typical output ri se/fall time (20% ? 80%, v ddext = min) load capacitance ? pf 2 5 -5 0 210 30 60 90 120 150 180 20 15 10 5 nominal y = 0.0835x - 2.42 o u t p u t d e l a y o r h o l d ? n s load capacitance ? pf 16.0 8.0 0 0 200 20 40 60 80 100 120 140 160 180 14.0 12.0 4.0 2.0 10.0 6.0 fall time rise time y = 0.0743x + 1.5613 r i s e a n d f a l l t i m e s ? n s ( 0 . 6 9 4 v t o 2 . 7 7 v , 2 0 % t o 8 0 % ) y = 0.0414x + 2.0128 load capacitance ? pf 16.0 8.0 0 0200 20 40 60 80 100 120 140 160 180 14.0 12.0 4.0 2.0 10.0 6.0 fall time rise time y = 0.0773x + 1.4399 r i s e a n d f a l l t i m e s ? n s ( 0 . 6 9 4 v t o 2 . 7 7 v , 2 0 % t o 8 0 % ) y = 0.0417x + 1.8674 table 37. airflow over package versus ( ..) 0 200 00 () 1 1 6.. 1. 15.2 1. t case t amb pd ca () + =
?56? ADSP-21161N rev. 0 225-ball metric mbga pin configurations table 38. 225-lead metric mbga pin assignments pin name pbga pin number pin name pbga pin number pin name pbga pin number pin name pbga pin number nc a01 clk_cfg0 n13 sdclk0 p10 br3 r0 bmstr a02 add 14 red p11 rd r0 bms a03 dmar1 15 clki p12 clkout r0 spids a04 trst b01 dqm p13 hbr r10 eboot a05 tdi b02 agd p14 hbg r11 lboot a06 rpba b03 dmar2 p15 clkdbl r12 sclk2 a0 mosi b04 tms c01 tal r13 d3b a0 s0 b05 emu c02 sdwe r14 l0dat4 a0 sclk1 b06 gd c03 c r15 l0ack a10 d2b b0 spiclk c04 tdo d01 l0dat2 a11 d3a b0 d0b c05 tck d02 l1dat6 a12 l0dat b0 d1a c06 lag11 d03 l1clk a13 l0clk b10 d2a c0 miso d04 l1dat2 a14 l0dat1 b11 s2 c0 sclk0 d05 c a15 l1dat4 b12 s3 c0 d1b d06 lag10 e01 l1ack b13 l0dat6 c10 s1 d0 reset e02 l1dat0 b14 l1dat c11 ddit d0 lag e03 rstout 1 b15 l1dat3 c12 sclk3 d0 d0a e04 lag5 01 l1dat1 c13 l0dat5 d10 ddet e05 lag 02 data45 c14 l0dat3 d11 ddit e06 lag 03 data4 c15 l1dat5 d12 ddet e0 lag6 04 lag1 g01 data42 d13 ddit e0 ddit 05 lag2 g02 data46 d14 ddet e0 gd 06 lag4 g03 data44 d15 ddit e10 gd 0 lag3 g04 lag0 h01 ddet e11 gd 0 ddet g05 irq 0h02 l0dat0 e12 gd 0 gd g06 ddit h03 data3 e13 gd 10 gd g0 irq 1h04 data43 e14 ddit 11 gd g0 ddit h05 data41 e15 data3 12 gd g0 gd h06 irq 2 01 data40 13 gd g10 gd h0 id1 02 data3 14 ddet g11 gd h0 id2 03 data36 15 data34 g12 gd h0 id0 04 timep k01 data35 g13 gd h10 ddet 05 addr22 k02 data33 g14 ddit h11 gd 06 addr20 k03 data32 g15 data2 h12 gd 0 addr23 k04 addr1 l01 data2 h13 gd 0 ddit k05 addr1 l02 data30 h14 gd 0 gd k06 addr21 l03 data31 h15 gd 10 gd k0 addr2 l04 addr16 m01 ddet 11 gd k0 ddet l05 addr12 m02 data26 12 gd k0 ddit l06 addr1 m03 data24 13 gd k10 ddet l0 addr6 m04 data25 14 ddit k11 ddit l0 addr0 m05 data2 15 data22 k12 ddet l0 ms1 m06 addr14 01 data1 k13 ddit l10 br6 m0 addr15 02 data21 k14 ddet l11 ddet m0 addr10 03 data23 k15 cas l12 wr m0 addr5 04 addr13 p01 data20 l13 sda10 m10
?57? rev. 0 ADSP-21161N addr[1] n05 addr[9] p02 data[16] l14 ras m11 ms0 06 addr p03 data1 l15 ack m12 br5 0 addr4 p04 c r01 data1 m13 br2 0 ms2 p05 addr1 r02 dmag m14 brst 0 sbts p06 addr r03 dmag m15 sdcke 10 br4 p0 addr3 r04 cs 11 br1 p0 ms3 r05 clkcg1 12 sdclk1 p0 pa r06 1 rstout x 12 l 03 10 11 figure 43. 225-lead metric mbga pi n assignments (bottom view, summary) table 38. 225-lead metric mbga pin assignments (continued) pin name pbga pin number pin name pbga pin number pin name pbga pin number pin name pbga pin number vddint vddext gnd 1 agnd avdd signal 1 use the center block of ground pins to provide thermal pathways to your printed circuit board ground plane key: 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 r p n m l k j h g f e d c b a
?58? ADSP-21161N rev. 0 outline dimensions the ADSP-21161N comes in a 17mm 1 225 15 . (). 225 (225) 1 1 225 (). 21161100 0 +5 100 1 1. . 21161100 0 +105 100 1 1. . 1.0 1. 151. 2. 0.25 . . 0.10 . 1.10 0.20 0.0 0.60 0.50 ( ) 0.0 1.00 1.00 1 2 5 6 10 11 12 1 15 1 1.00 ( ) 1.20 1.00 16.0 1.20 1.00 16.0 ( ) ( ) 1
?59?
?60? printed in u.s.a. c02935-0-7/02(0)


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